1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices, in which two kinds of conductive and insulating thin films are formed on a semiconductor substrate.
2. Description of the Prior Art
In such a semiconductor device comprising two kinds of conductive and insulating thin films formed on a semiconductor substrate, the conductive thin film is utilized as a wiring layer or as the material for reducing the resistance while the insulating film is used as the insulating material or the dielectric material.
When the insulating film is to be applied as the dielectric material, there is generally employed a film of silicon dioxide (SiO.sub.2) and when the conductive film is to be applied as the wiring layer, there is generally employed an aluminum layer or a polycrystalline silicon layer.
As a semiconductor device comprising conductive and insulating thin films formed on a semiconductor substrate, for example, there have been provided semiconductor memory devices called dynamic random access memory (hereinafter referred to as D-RAM) in which a plurality of memory cells each consisting of a MOS field effect transistor and a capacitor are formed on a substrate. In the D-RAM, the insulating film is employed as the dielectric material for the capacitor while the conductive film is applied as a wiring layer.
In recent years, such D-RAMs are subjected to high scales of integration, i.e., fine construction, and thus reduction of areas in which the capacitors are formed. For preventing malfunction of such D-RAMs, there have been proposed D-RAMs employing composite oxide as the dielectric material for the capacitor, which comprises silicon dioxide and an oxide of a metal having a high melting point such as tantalum, in order to increase the storage amount of electric charges. The dielectric constant of such a metal oxide is over twice as large as that of silicon dioxide. Examples of such D-RAMs are disclosed in "Interfacial Oxidation of Ta.sub.2 O.sub.5 -Si Systems for High-Density D-RAM" by T. Kato et al; 1983 Symposium on VLSI Technology, page 86 and Japanese Patent Laying-Open Gazette No. 24541/1982.
FIG. 4 is a cross-sectional view of the D-RAM as disclosed in the Japanese Patent Laying-Open Gazette No. 24541/1982. In the D-RAM as shown in FIG. 4, a MOS field effect transistor is formed with a drain portion 8 and a source portion 9 both provided on one main surface of a p-type silicon substrate 1 and a gate electrode 7a consisting of a polycrystalline silicon film provided on the upper surface of a silicon dioxide film 6, and a capacitor is formed with the p-type silicon substrate 1, a composite oxide film 5 composed of tantalum oxide and silicon oxide and a polycrystalline silicon film 7b, while wiring layers are formed with aluminum thin films 11a and 11b.
In a method of manufacturing the D-RAM having the aforementioned structure, a silicon dioxide thin film 3 is formed on the upper surface of a p-type silicon substrate 1 which is provided with a thick field oxide film 2, and a tantalum thin film 4 is formed by sputtering on the upper surface of the silicon dioxide film 3 as shown in FIG. 1.
Then, as shown in FIG. 2, the silicon dioxide film 3 and the tantalum thin film 4 are selectively removed in a desired pattern by a photo etching method and thermal processing is performed to convert the residual portions of the silicon dioxide thin film 3 and the tantalum thin film 4 into a composite oxide film 5, while a silicon dioxide thin film 6 is formed on the exposed portion of the silicon substrate 1.
Then, as shown in FIG. 3, a polycrystalline silicon thin layer serving as a gate electrode 7a of a MOS field effect transistor and one electrode 7b of a capacitor is formed in the selected pattern, followed by formation of a drain portion 8 and a source portion 9 by ion implantation with about 80 KV.
Thereafter a silicon dioxide thin film 10 is formed over the entire surface of the substance, with contact holes formed in portions of the silicon dioxide thin film 6 located on the drain portion 8 and the source portion 9, followed by formation of a wiring layer 11a of an aluminum thin film to be connected with the source portion 9 and a wiring layer 11b of an aluminum thin film to be connected with the drain portion 8, thereby to obtain a substance in the structure as shown in FIG. 4.
However, while the storage capacity of the capacitor is increased in the D-RAM having the aforementioned structure, there are required steps of forming the dielectric material portion of the capacitor alone, i.e., the step of forming the silicon dioxide thin film 3, the step of forming the tantalum thin film 4 and a step of performing mask alignment etc., leading to increase in the number of the steps.
With respect to the MOS field effect transistor, on the other hand, there is proposed in Japanese Patent Laying-Open Gazette No. 88783/1979 employment of a laminated foil formed by providing a film of a silicide of a metal having a high melting point on a polycrystalline silicon film as a wiring layer to be connected to each of a gate electrode and a source portion.
Then the laminated foil of the silicide of the metal having a high melting point provided on the polycrystalline silicon film as proposed by the Japanese Patent Laying-Open Gazette No. 88783/1979 is applied to the wiring layer 11a to be connected with the source portion 9 (and the wiring layer 11b to be connected with the drain portion 8) in the aforementioned Japanese Patent Laying-Open Gazette No. 24541/1982, the polycrystalline silicon layer and the layer of the metal silicide are formed after formation of the MOS-type transistor and the capacitor, whereby the steps are further increased in number.